1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device having multi-level interconnection layers and, more particularly, to a semiconductor integrated circuit device having a multi-level interconnection structure in which upper and lower interconnection layers intersect with each other.
2. Description of the Prior Art
In conventional semiconductor integrated circuit device, a multi-level interconnection structure having multi-level interconnection layers is employed to improve an integration degree. FIG. 1 shows a conventional grid-type interconnection layout in which a lower interconnection layer is formed on wafer 10 along prospective interconnection lines. Referring to FIG. 1, broken lines 101 to 105 represent grid lines along which the lower interconnection layer can be formed, and dash lines 201 to 205 represent grid lines along which the upper interconnection layer can be formed. In FIG. 1, only the lower interconnection layer is shown, and the upper interconnection layer is omitted.
The lower interconnection layer is constituted by pattern 11 formed along grid line 101, patterns 21 and 22 formed along grid line 102, patterns 31 and 32 formed along grid line 103, patterns 41 and 42 formed along grid line 104, and pattern 51 formed along grid line 105. On grid lines 102, 103, and 104, patterns are partially disconnected.
The multi-level interconnection with the above arrangement has the following three problems.
The first problem is a configuration of the surface of an insulating film formed on the lower interconnection layer. A section of a structure along line 201 in FIG. 1 is shown in FIG. 2A. In general, when an insulating material is deposited on the surface of the wafer having steps, the insulating film having a substantially equal thickness is formed on upper, side, and bottom surfaces of the steps. Therefore, as shown in FIG. 2A, when patterns 11, 21, 31, 41, and 51 are formed on wafer 10 at a constant pitch, an insulating film having a thickness which is 1/2 or more of an interval between the patterns is formed, so that grooves at the intervals of the patterns are buried with the insulating film. As a result, the surface of the insulating film can be substantially flattened.
When the pattern is partially discontinued, as in pattern 31, patterns do not exist at equal intervals in, e.g., a structure along line 204, as shown in FIG. 2B, but the interval between patterns 21 and 41 is larger than intervals between other adjacent patterns. In this large groove, a step is undesirably formed on the surface of the insulating film formed in the groove. Since this step is substantially vertical, when an upper interconnection layer is formed on this insulating film 60, disconnection may occur in the upper interconnection layer. Therefore, a manufacturing step for flattening insulating film 60 is required. In this case, the ratios of the depth and the width of the grooves, i.e., aspect ratios are different in large and small regions wherein the pattern of the lower interconnection layer does not exist. Therefore, a sufficient flattening step is required in consideration of the worst case as the basis, thereby increasing a manufacturing cost.
The second problem is a loading effect during etching for forming a first interconnection layer. In normal anisotropic etching, a polymer film consisting of carbon, oxygen, fluorine, and the like is attached to a side wall of an etched portion to serve as an etching protection film, and side etching is prevented, thereby obtaining a substantially vertical shape. In this case, since the carbon is supplied from a resist, side etching can be prevented near a dense resist pattern. However, in a sparce resist pattern, side etching is advanced because carbon is not sufficiently supplied. In particular, in a portion near the peripheral portion of a chip and having a low interconnection density, the interval between adjacent interconnection patterns is large and the interconnection patterns tend to be isolated. In the worst case, disconnection of the interconnection layer may occur.
The third problem is that a capacitance of an interconnection pattern is varied depending upon the presence/absence of adjacent interconnection patterns. In recent semiconductor elements, an operation speed largely varies depending upon the value of the interconnection capacitance. These interconnection capacitances are roughly classified into a capacitance with respect to ground and a capacitance between adjacent interconnection patterns. As an interval between adjacent interconnection patterns is decreased with the miniaturization of elements, a ratio of the capacitance between adjacent interconnection patterns is increased.
An interconnection capacitance and hence the operation speed of the element largely change depending on whether an adjacent interconnection pattern exists. Design for a semiconductor integrated circuit device must be performed in consideration of the above difference. When a large scale integrated circuit which cannot be designed without employing an automatic placement and routing programs by a computer is designed, the above consideration is impractical. Note that, in an integrated circuit having uniform capacitances, the operation speed can be easily estimated and the circuit can be operated at optimal timings as compared to an integrated circuit in which a circuit having a large interconnection capacitance due to adjacent interconnection patterns and a circuit having a small interconnection capacitance without adjacent interconnection patterns are mixed.
Although a layout method in which an interconnection layer is formed on grid-type interconnection lines is exemplified and described as described above, a general layout method without employing the grid-type interconnection line also has the same problems. More specifically, when a general layout method as shown in FIG. 3 is employed, in a portion in which lower interconnection layer patterns 11a and 11b are arranged at a small interval, i.e., a portion along alternate long and short dash line 201a, insulating film 60 has a flat surface, as shown in FIG. 4A. However, in a portion including a part having a small width, e.g., lower interconnection layer pattern 11a and therefore having a large interval between the part having a small width of pattern 11a and lower interconnection layer pattern 11b, i.e., a portion along alternate long and short dash line 201b, the surface of insulating film 60 is uneven, as shown in FIG. 4B. For this reason, it is difficult to form upper interconnection layer patterns 21a and 21b .